The hiring process at Cadence Design Systems takes an average of 14 days when considering 1 user submitted interviews across all job titles. Candidates applying for Digital IC Verification Intern had the quickest hiring process (on average 14 days), whereas Digital IC Verification Intern roles had the slowest hiring process (on average 14 days).
Basics of C++, Graphs, etc. were asked. The interviewer was helpful and knowledgeable throughout. Brush up on all your C and C++ basics before stepping in after the resume shortlisting round
I applied through a staffing agency. The process took 4 days. I interviewed at Cadence Design Systems (Noida) in Aug 2021
Interview
Interview process was online. There were 2 technical and 1 Managerial round as I applied through referral. First round has Digital, Verilog, SystemVerilog and UVM questions to check how strong in basics.
The second round was bit difficult where more in depth practical or application knowledge was tested along with some puzzles.
The third round was basic Managerial round where few HR questions and few technical questions on Verilog basics and timing were asked.
Interview questions [1]
Question 1
1. Basic Digital questions
2. Event scheduler question in Verilog
3. Concepts of SV - Constraints, Assertions, Functional coverage
4. Concepts of UVM
5. Basics of PERL and LINUX
Basic SV questions with coding. Too many questions on IP. Good interview with manager and one team. 1 phone round and 1 video coding round. Questions about your experience overall