Different ways of modeling FSM in Verilog Use of Casex in Verilog Coding Verilog coding was asked for many counters Timing diagrams of some Digital elements
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Besides the information listed on your resume, is there any additional information you would like to provide for us to consider you further for this position?
Describe the basic flow of DFT and the problem you met in the project
Tell me something about the asic flow
How do you access a register and confirm it is 12 bit or not?
Can u draw mod-6 down counter.Write design flow of ASIC,difference between $display,$strobe,$monitor.
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
cross domain clocks design example
Most unexpected question is which part of your Ph.D work makes you proud the most.
Computer Architecture, Verilog
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