whats the ad and disad of using large cache and small cache
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
Clock skew? Good or bad for a circuit with 2 flops and combinational logic in between.
There are two questions, one is about FSM, you should design a FSM with 5 bit, its function is to counter the even number of 0 or 1, e.g. 2, 4, 6....
What will happen if a default case is not used in a case statement?
Check the awareness of applying pre and post randomization in variables in uvm_object.
5/6 interviewers asked about past work experience, design problems, and analysis of circuits. One interviewer asked general get-to-know you questions.
Also asked some C++
Design group people are very very nice. In verification group, was asked knowledge in undergraduate school, like communication principle and analog circuit questions. I almost forgot the communication principle, but he kept on asking.... I kind of hate this guy
It was mainly behavior questions about resume
Fifo functionality and verilog code to write
Viewing 101 - 110 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerSenior Vlsi Design EngineerVlsi EngineerAsic Physical Design EngineerSenior Asic Design EngineerSoc Design EngineerRtl Design EngineerHardware Asic Design EngineerPhysical Design EngineerSenior Dft-ingenieurHardware Engineering ManagerHardware Asic Ontwerp IngenieurSenior Fpga Design EngineerFpga Design EngineerFpga Development EngineerSenior Hardware Design EngineerSenior Asic Fpga Design EngineerAsic Design Verification Engineer