Round 1 1- Two to Three Q's on Projects done 2- Designing Q - Consider inputs coming at every clock. I want the output at time = t to give me sum of all nos coming before that time. (Adder is normal adder with latency 1) 3- Designing Q - Consider the same output needed, but adder has a latency of 2. So input is taken at every clock and output is given at every clock. But Input at t=0 is received at output at t=2, input at t=1 is received at output at t=3...
-Make a AND/OR gate out of muxes -Count the number of 1's in a 7 bit number using only full adders
QUestions were very simple like given a program whats is the output, phases in UVM, implementimg gates using muxes etc.
1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
FIFO questions
Design OR gate using MUX
Data Structures: Linked Lists , Binary Search Tree Concept and Complexity. Hash Tables in C++/Python. C++: Private vs Public Pass by Value vs Pass by Reference Pointer vs Reference Computer Architecture: Pipelining What is Cache & Cache Performance (Hardware & Software) Cache Architecture Virtual Adress Address Translation TLB Explain your Class/Internship Project
implement 3 input nand using 2:1 muxes
Read a file in unix and count for the particular word in file using single command script.
design state machine to detect 1101 sequence with overlap
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