Design a clock divide-by-3 circuit with 50% duty cycle
Design Coordinator Interview Questions
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question on clock gating- for an 8-bit wide register ,what are the different ways in which clock gating can be implemented to reduce overall power
Which gate would you prefer in a design? Nand or Nor? why?
Just scenario-based. Asked about ISD theories and practices. Typical.
How does the computer start?
What is MOESI?
How to fix the hold-time violation after the chip was fabricated?
Why do you want to change your job?
there's a room with lots of balloons filled with He, how to break them all. Name as much methos as possible
1) Implement Linked list in hardware 2) LIFO using queues only
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