UVM Concepts and Work Experience of previous project
Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
How we can integrate agents without them generating stimulus
7 questions total. One about arm products, 2 about coding in any programming language you want and 2 about coding in VHDL. Last question was if I Had any questions.
Is there anything else you would like to add?
Draw a block diagram of a simple processor and explain how a particular instruction will flow through it.
Assertions,SV OOPS, Comp Arch
How to design an Accumulator. How to generate ramp signal in verilog. What are start and stop bits. Min. delay and Max. delay.
What is ASIC Design flow?
Digital Electronics:- FSM, Register, Flip flop, MUX. Verilog:- write program for FSM, clock generator, mux. SystemVerilog:- programming question based on randomisation. UVM:- write code for driver sequencer ,Tlm ports.
Write some code to efficiently sort three input number from hardware perspective
Viewing 1061 - 1070 interview questions