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design a module using any HDL that recives pulses and the goal is to detect 10 pulses within 100 cycles, the interesting part is the ability to detect 10 ulses from the moment we get each pulse. for example: lets say we get a pulse start counting the 100 cycles, if we reach 10 pulses before the time ends then start counting from the time we received the second pulse until the eleventh and so on.
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FPGA Engineer

Interviewed at AST SpaceMobile

3.1★
Jun 21, 2023

design a module using any HDL that recives pulses and the goal is to detect 10 pulses within 100 cycles, the interesting part is the ability to detect 10 ulses from the moment we get each pulse. for example: lets say we get a pulse start counting the 100 cycles, if we reach 10 pulses before the time ends then start counting from the time we received the second pulse until the eleventh and so on.

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