FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
I could not reveal the questions
The interview began with fundamentals like race conditions, reset types (synchronous vs. asynchronous), and their advantages. I was then asked to write RTL code for a basic flow, with the interviewer gradually increasing complexity by adding registers and FIFO elements. In the final part, I explained my projects in detail, focusing on my contributions, design decisions, and verification approach.
Hiring managers asked about project details and tools. He was expected digital design solutions and CDC related topics. Lint and Lowpower design questions asked and given FIFO calculations. Current company job roles and responsibilities and challenges in current project
how to handle pressure wheneverwork pressure increases
synchronization of multiple control signals FIFO Depth calculation
sync vs asyc rst
Questions were standard interview question on synthesis and lint
Most questions were from digital electronics and verilog
Design a module to return trigonometric sine value. Other question is related to the designing of the State Machine with the specified requirements.
Viewing 141 - 150 interview questions