FIFO design
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
How to implement not with nand/nor gates
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Write the verilog code for a counter then change reset to asychronized.
Constraint randomization based question linking to AXI and memory filling
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
Questions on the resume. SV constructs, FIFO depth, STA questions
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Sequence detector with FSM Synchronization Cache
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