Describe a time when you need to gather information from different sources to troubleshoot an issue.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Write verilog code for D ff.
Describe the projects you have worked on.
write a code to extract input and outputs
c++ swap, pipeline
They checked your resume and asked the questions related to your classes.
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Mostly RCG level questions.
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
Metastability
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