What's pipelining? What's cache coherency?
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
My previous experience, basic assertions and fifo programming
What is the difference between task and function
How do you access a register and confirm it is 12 bit or not?
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Computer Architecture, Logic design, validation, software, behavioral.
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
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