Asked lots of questions about Cache and Virtual Memory, including Cache set, index, associativity, etc. CPU superscalar, Out of Order, etc. Address translation, aliasing problem
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
1. constraints 2. assertions 3. UVM topology
Uvm phases and explain them
* Have you used UVM? * What is your knowledge level of SystemVerilog?
return count of characters in a string, in C
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