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Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
Asked me to tell about myself, past work I’ve done, what do I expect from my new team, manager, etc.
Questions on interface, clocking blocks, assertions, uvm, X propagation.
Dont remember much but mostly code deep dives and situational questions related to work.
Describe what a virtual function does?
I was asked to write system verilog constraints for a variety of random stimulus needs.
Register renaming
Test cases for a 2 input, 2bit adder.
What is the difference between blocking and non-blocking assignments?
1. C++, OOP 2. python: dictionary, swap values 3. Systemverilog: fork join 4. delete repeated element in an array 5. FIFO depth 6. find SA0/SA1 amoung 128 wires in minimal steps
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