Verify a packet processing DUT where packets coming in have a certain priority.
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
What is the difference between blocking and non-blocking assignments?
I was asked to write system verilog constraints for a variety of random stimulus needs.
Questions on C++, Perl, System Verilog.
Register renaming
Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
Write verilog code for any flipflop. variations were also asked.
The asked about past work experience.
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
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