Draw a state machine that accepts the sequence 101
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
FIFO Depth, SV assertions, Multi-threading and OOP concepts
Given read and write freq, how to calculate FIFO depth?
Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
- about SV, FIFO design, arbiter design
questions about OVM process
Find the number of '5''s in a rolling window of size 10. Flag an error when the count>4
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
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