About digital electronics for VLSI domain
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
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My projects which was relevant to job role
Asked me questions on Tessent tool
My experience was bad in 2 rounds otherwise good in other 3 rounds.
Basic question on UVM?
implement blackjack with classes in python
Write code for a UVC mimicing a memory . Reactive sequence in UVM
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